The continuing popularity of portable electronic devices presents manufacturers with significant challenges. Increasing capability of electronic devices is moderated by considerations of cost, size, weight, and battery life. These considerations have increasingly resulted in higher levels of semiconductor integration. Thus, portable electronic devices frequently embed memory, control, signal processors, and other circuit functions on a single integrated circuit. Further optimization of these portable electronic devices dictates even greater reduction in geometric feature sizes and spaces between these geometric features. Shrinking feature sizes require lower supply voltages to limit maximum electric fields. Transistor leakage must be minimized to reduce standby current and prolong battery life. Even with lower supply voltages, however, special considerations are required for reliable device operation.
One problem of source/drain resistance was addressed by Yamazaki, U.S. Pat. No. 5,547,888, which is incorporated herein by reference in its entirety. Therein, Yamazaki discloses a disadvantage of symmetrical lightly doped drain (LDD) transistors in a static random access memory (SRAM) cell. Yamazaki discloses that hot carrier reliability only depends on the drain structure and not the source structure. Yamazaki also discloses that a source LDD region may limit on current of the transistor and require a greater channel length. Yamazaki discloses a method of masking the source region of the transistor during the LDD implant to produce an asymmetrical transistor with only a drain LDD implant.
A problem of punch through with short channel lengths was addressed by Wang et al., U.S. Pat. No. 6,566,204, which is incorporated herein by reference in its entirety. Punch through occurs when source and drain depletion regions of a field effect transistor extend across the channel. Under these conditions, the overlying control gate can no longer control current flow between the source and drain. Pocket implants were previously used to locally increase bulk concentration in the channel region of the field effect transistor, thereby limiting depletion region width and resulting punch through. Pocket implants in the drain region, however, limited drive current and increased threshold voltage. Wang et al. disclosed that punch through could be effectively curtailed with an asymmetrical pocket implant adjacent the source of the field effect transistor. Wang et al. further disclose a method of blocking the pocket implant at the drain of the field effect transistor with a mask pattern in close proximity to the control gate of the field effect transistor. The close proximity of the mask pattern selectively blocks the angled pocket implant but permits implantation of source/drain zones without the need for additional masking steps.
Lien, U.S. Pat. No. 5,790,452, is incorporated herein by reference in its entirety. Lien applied an angled pocket implant to a static random access memory (SRAM) cell to solve a different problem. Referring to FIG. 1A, there is a schematic diagram of an SRAM cell 100 of the prior art disclosed by Lien as FIG. 2. The SRAM cell includes a latch formed by load resistors 101 and 102 and N-channel drive transistors 103 and 104. The latch is connected between positive supply voltage Vdd 112 and ground or Vss 114. The supply voltage levels Vdd and Vss are also referred to as high and low levels, respectively, for simplicity. Storage nodes 116 and 118 of the latch are connected to bitlines 108 and 110 by access transistors 105 and 106, respectively.
Lien disclosed two conflicting modes of operation of the SRAM cell. During write-disturb mode the SRAM cell of FIG. 1A is not accessed and the wordline 120 is low. Storage nodes 116 and 118 are low and high, respectively, and complementary bitline 110 is low. Under this condition, access transistor 106 has significant subthreshold leakage. Lien discloses a high threshold voltage, therefore, is desirable to limit subthreshold leakage when storage node 118 is high and bitline 110 is low. During read mode bitlines 108 and 110 are both initially high and wordline 120 is high. When the latch storage nodes 116 and 118 are low and high, respectively, Lien discloses an advantage to a low threshold voltage on access transistor 106. This low threshold voltage of access transistor 106 provides a higher voltage at storage node 118 and, therefore, a greater gate voltage at drive transistor 103. Thus, Lien discloses an advantage of a low threshold voltage of access transistor 106 when bitline 110 is positive with respect to storage node 118 in read mode.
Referring to FIG. 1B, there is a cross section of N-channel access transistor 106 of the prior art as disclosed by Lien at FIG. 3. The access transistor 106 includes N+ source/drain region 118 connected to storage node 118 and N+ source/drain region 110 connected to bitline 110. An N-type lightly doped region 132 extends from N+ source/drain region 118 into the channel region under control gate 134. A P-type pocket implant encloses N+ source/drain region 110. When the N+ drain 118 is positive with respect to N+ source 110, Lien discloses access transistor 106 has a high threshold voltage. Alternatively, when the N+ drain 110 is positive with respect to N+ source 118, access transistor 106 has a low threshold voltage.